1. Field of the Invention
The present invention relates to a display device for displaying a screen.
2. Description of Related Art
Various types of display devices such as the TFT (Thin Film Transistor) liquid crystal display device, the simple matrix liquid crystal display device, the electro luminance (EL) display device and the plasma display device are widely spread. On a display device, a screen is displayed. In recent years, the display size tends to become larger in order to display large size images.
However, as the size of a display device becomes larger, the signal delay caused by resistances or capacitances of scanning lines of the display device becomes larger. This delay causes a lag of the timing of outputting data on screen, which may cause a defect in the display screen. Therefore, it is desired to prevent such a defect.
As an example of the technique for preventing this problem, Japanese Laid-Open Patent Application JP-P2000-250068A (referred to as Patent Document 1) describes a TFT liquid crystal display device 100. As shown in FIG. 1, this TFT liquid crystal display device 100 includes: a glass substrate 101, a scanning driver (gate driver) 108, a drain driver 107, and a display unit (liquid crystal panel).
The liquid crystal panel includes a plurality of pixels arranged on a glass substrate 101 in a matrix form.
Each of the plurality of pixels includes: a thin film transistor (TFT) 102, and a pixel capacitor 105. The pixel capacitor 105 includes a pixel electrode and an opposite electrode opposing the pixel electrode. The opposite electrode is grounded. The TFT 102 includes: a drain electrode 103, a source electrode 104 connected to the pixel electrode, and a gate electrode 106.
The TFT liquid crystal display device 100 further includes: a k-number of scanning lines (gate lines) 108G1 to 108Gk (where k is an integer of two or larger).
To the gate electrodes 106 of the TFTs 102 of the pixels in a plurality of rows, the k-number of gate lines 108G1 to 108Gk are respectively connected.
To the gate driver 108, the k-number of gate lines 108G1 to 108Gk described above are connected.
The TFT liquid crystal display device 100 further includes a j-number of data lines 107D1 to 107Dj (where j is an integer of two or larger).
To the drain electrodes 103 of the TFTs 102 of the pixels in a plurality of columns, the j-number of data lines 107D1 to 107Dj are respectively connected.
To the drain driver 107, the j-number of data lines 107D1 to 107Dj described above are connected.
The TFT liquid crystal display device 100 further includes a dummy gate line 109.
The drain driver 107 includes a latch terminal 112.
The dummy gate line 109 is provided on the glass substrate 101 in parallel to the k-number of gate lines 108G1 to 108Gk. To the gate driver 108, one end (input end) 109a of the dummy gate line 109 is connected as a 0-th gate line. The other end (terminal end) 109b of the dummy gate line 109 is connected to the latch terminal 112.
To the gate driver 108, selection clock signals (VCK, VSP) are supplied. These selection clock signals (VCK, VSP) are defined as clock signals for selecting the gate line 108G1 in one horizontal period.
The gate driver 108, in response to the selection clock signals (VCK, VSP), outputs a selection signal to the gate line 108G1. At this point, to the gate line 108G1, the selection signal is transmitted in order from one end to the other end thereof, and the TFTs 102 of a j-number of pixels corresponding to the gate line 108G1 are turned on by the selection signal supplied to the gate electrodes 106.
Moreover, to the dummy gate line 109, the clock signal VCK is supplied. At this point, to the dummy gate line 109, the clock signal VCK is transmitted in order from the input end 109a to the terminal end 109b thereof. As a result, the clock signal VCK transmitted to the terminal end 109b of the dummy gate line 109 is transmitted as a latch signal LP to the latch terminal 112 of the drain driver 107.
To the drain driver 107, a clock signal HCK and a j-number of one-line display data DAT are supplied.
The drain driver 107, in accordance with the clock signal HCK and the latch signal LP, outputs the j-number of one-line display data DAT to the j-number of data lines 107D1 to 107Dj. At this point, the TFTs 102 of the j-number of pixels corresponding to the gate line 108G1 and the j-number of data lines 107D1 to 107Dj are on. Thus, in the pixel capacitors 105 of the pixels corresponding to the j-number of data lines 107D1 to 107Dj, the j-number of one-line display data DAT are respectively written and held until the next writing. Consequently, the j-number of one-line display data DAT are displayed.
With the TFT liquid crystal display device 100 explained above, when the gate driver 108 has outputted the selection signal to the gate line 108G1, this selection signal is delayed by resistance and capacitance of the gate line 108G1. In this case, when the gate driver 108 has outputted a selection signal to the dummy gate line 109, this selection signal is delayed by resistance and capacitance of the dummy gate line 109. The delay time from when the gate driver 108 has outputted the selection signal to the dummy gate line 109 to when the selection signal is transmitted to the terminal end of the dummy gate line 109 is represented by Δ t.
The delay time Δ t shows the timing (transmission timing) at which the selection signal inputted from the input end transmits to the terminal end of the dummy gate line 109.
The clock signal VCK transmitted to the terminal end 109b of the dummy gate line 109 is transmitted as the latch signal LP to the latch terminal 112 of the drain driver 107 while being delayed by the delay time Δ t. The drain driver 107, in accordance with the clock signal HCK and the latch signal LP, outputs the j-number of one-line display data DAT to the j-number of data lines 107D1 to 107Dj. Therefore, the delay time Δt determines the timing (output timing) of outputting data by the drain driver 107.
Consequently, in the TFT liquid crystal display device 1 explained above, the timing of outputting data by the drain driver 107 can be adjusted to the delay by the resistance and capacitance of the gate line 108G1. As a result, a displaying defect caused by the signal delay can be prevented in the TFT liquid crystal display device 1.